1. Technical Field
The present invention relates to decoders for recovering digital data from a transmitted analog signal, more particularly to a multiple layer transition (MLT-3) decoder configured for receiving a 125 Mb/s MLT-3 encoded signal from a 100BASE-TX Ethernet (IEEE Standard 802.3u) transmission medium for decoding into a two-level Non-Return to Zero Interface (NRZI) digital signal in a physical layer transceiver.
2. Background Art
Local area networks use a network cable or other network media to link nodes (e.g., workstations, routers and switches) to the network. Each local area network architecture uses a media access control (MAC) enabling network interface device at each network node to share access to the media.
Physical (PHY) layer devices are configured for translating digital packet data received from a MAC across a standardized interface, e.g., a Media Independent Interface (MII), into an analog signal for transmission on the network medium, and reception of analog signals transmitted from a remote node via the network medium. An example is the 100BASE-TX Ethernet (IEEE Standard 802.3u) receiver, configured for receiving a three-level MLT-3 encoded analog signal at a 125 Mb/s data rate. For example, FIGS. 1A, 1B and 1C are diagrams illustrating an original NRZI-encoded digital signal for transmission on the media, an encoded MLT-3 signal generated at the transmitting PHY layer for transmission on the network medium, and an MLT-3-encoded analog signal having been transmitted by the network medium and received by a PHY transceiver at a destination node. As shown in FIG. 1A, the original bilevel digital signal, encoded as an NRZI signal, is encoded into the three-level MLT-3 signal of FIG. 1B before transmitting the digital information to the receiving station. On the receiving side, the MLT-3 encoded signal of FIG. 1B encounters transmission loss, for example high frequency attenuation, resulting in the received MLT-3 signal of FIG. 1C. Hence, the 100BASE-TX Ethernet (IEEE 802.3u) receiver must recover the digital information from the received MLT-3 signal of FIG. 1C.
FIGS. 2A, 2B and 2C illustrate one proposal for recovering the NRZI signal from the received MLT-3 signal. In particular, FIG. 2A is a diagram illustrating a prior art decoder that decodes the received MLT-3 signal of FIG. 2B to obtain the NRZI signal of FIG. 2C. As shown in FIG. 2A, the prior art decoder includes two comparators 10a and 10b, and an OR gate 12 to convert the received MLT-3 signal into an NRZI-format signal. Specifically, each comparator 10 receives the received MLT-3 signal (C) and an inverted copy of the received MLT-3 signal (CB), where the signal CB has an inverse polarity relative to signal C, as shown in FIG. 2B. In particular, comparator 10a receives the C signal and the CB signal at a non-inverting input and an inverting input, respectively, whereas comparator 10b receives the C signal and the CB signal at inverting and non-inverting inputs, respectively. The comparators 10a and 10b are positive edge triggered, hence the comparators output a logical zero (e.g., no signal) if the values of C and CB are equal (e.g., equal to zero volts). If the signal C exceeds signal CB by a prescribed threshold T.sub.a, as shown in FIG. 2B, the comparator 10a outputs a comparison signal 14 as a logical 1. In contrast, if signal CB exceeds signal C by a prescribed threshold Tb, the comparator 10b outputs a comparison signal 16 as a logical 1 to the OR gate 12.
Although the decoder circuit of FIG. 2A is relatively easy to implement, the circuit of FIG. 2A encounters numerous problems in actual implementation. Noise encountered during the transmission of the MLT-3 encoded signal requires that the threshold values of the comparators 10a and 10b be set to a non-zero value. The ideal comparator threshold is half of the peak value, namely between the middle point P.sub.1 and the positive/negative peaks P.sub.2 /P.sub.3. In practical design, however, such a comparator with controlled thresholds that can adapt to signal peak values is not easy to implement in the circuit of FIG. 2A.
In addition, the MLT-3 signal of FIG. 2B, having encountered high frequency attenuation during transmission, has slow rise-fall edges, e.g., a degraded slew rate. Hence, each comparator 10a, 10b will also generate an output signal 14, 16 having a reduced slew rate as a signal edge, as opposed to the ideal instantaneous (i.e., vertical edge). In addition, the precise point at which the input MLT-3 signals C and CB cross the thresholds T.sub.a and T.sub.b is varied due to the attenuated slew rate. Variations in the threshold voltage also affect the precise point at which the input signals C and CB cross the threshold. Hence, the precise location of the leading edge of the MLT-3 encoded signal as shown in FIG. 1B is difficult to identify.
Moreover, conventional comparators have threshold hysteresis, where the comparators do not have identical rising-edge thresholds and falling-edge thresholds. Hence, if the rising-edge threshold (T.sub.a ) is set at a peak voltage divided by 2 (e.g., 50 milli-volts), the falling-edge threshold (T.sub.c) may have a different value (e.g., 45 milli-volts) that affects when the comparator output signal is turned off. For example, if the rising-edge threshold is slower (e.g., 50 milli-volts) than the falling-edge threshold (e.g., 45 milli-volts), the resulting pulsewidth of the comparator signal will be narrower than ideal; conversely, if the rising-edge threshold is faster (e.g., 40 milli-volts) than the falling-edge threshold (e.g., 45 milli-volts), the resulting pulsewidth of the comparator signal will be wider than ideal. Hence, the threshold hysteresis present in comparators adversely affects the pulsewidth of the pulse 14 and 16 output by the comparators 10a and 10b, respectively.
These factors cause the comparators 10a and 10b to output a comparison signal at variable times, which introduces timing variations (i.e., jitter) into the decoded NRZI signal of FIG. 2C. Hence, the decoded NRZI signal may include jitter that may affect the accurate detection of the network clock, as well as accurate detection of the decoded data in a synchronous system.
FIGS. 3A and 3B illustrate an alternative MLT-3 decoder. The decoder of FIG. 3A includes buffers 14a and 14b, for example a unit-gain amplifier, and voltage offset supply sources 16a and 16b. Hence, the voltage sources 16a and 16b output the signals C.sub.o and CB.sub.o, respectively, as shown in FIG. 3B. Use of the unit-gain amplifiers 14 enables addition of a DC offset, which adds a degree of noise immunity to the comparators 18a and 18b, reducing the required threshold values. However, the additional stage of buffers 14a and 14b increases the propagation delay and reduces the input bandwidth of the decoder circuit, becoming a critical issue in relatively low speed CMOS circuit implementations, especially for 100BASE-TX Ethernet (IEEE 802.3u) applications.
FIGS. 4A and 4B illustrate still another conventional approach for performing MLT-3 decoding. Specifically, the MLT decoding circuit of FIG. 4A includes comparators 20a and 20b, where potential sources 22a and 22b are set according to the decoder threshold and the amplitudes of the differential input signals C and CB. However, the circuit of FIG. 4A provides poor performance of common mode noise rejection, unless the respective potentials P1 and P2 of voltage sources 22a and 22b can be derived to track the common mode noises in signals C and CB. In addition, bandwidth limitations are encountered if the decoder circuit of FIG. 4A is implemented in CMOS.